Nowadays silicon systems like micro-electrical-mechanical systems (MEMS), electroluminescent lamps or piezo amplifiers for example have handling voltages in the range of 100-150V. For switching these devices HV (high voltage) NMOSFET transistors can be used which are able to switch on the high side near VDD thereby avoiding parasitic drain/substrate current.
To allow large potential drops inside doped transistor regions a low doped epitaxial layer with large thickness is needed which makes this technology expensive.
To overcome this disadvantage and to reduce the device depth from the silicon surface, a careful design of the used wells must ensure that the electrical fields in the sensitive parts of the device are reduced, the device thereby staying compatible with the existing low voltage logic. These sensitive locations are in the area of the bird's beak (see BB in FIGS. 1 and 2) of the field oxide being arranged between source and drain regions, the area below the body well and near the corners of the device (3rd dimension). The key point for high side operation is to isolate the device channel from the p-doped substrate. Usually this is done by placing the body well inside an n-doped well. In general the distance between the body well and the substrate determines the isolation of the channel to the substrate. In addition a large such distance allows to bias source and body below or above substrate potential and reduces the beta parameter of the parasitic bipolar pnp transistor comprising p-body, DN well and p-doped substrate.
Normally the DN well used to situate the body therein is generated by a high temperature drive in step. This results in a typical well profile which has the highest concentration of doping and therefore the steepest body/DN junction close to the silicon surface.